Semiconductor devices, fabrication processes for manufacturing semiconductor devices, and associated test circuits and test structures are well known. On-chip test architectures are often used to check certain characteristics of a semiconductor device (such as a device that implements combinatorial or sequential logic) manufactured by a particular process. In this regard, the on-chip test structure is fabricated using the proposed manufacturing process, and with standard circuit modules, cell libraries, and the like. Consequently, the on-chip test structure can be exposed to controlled test conditions (e.g., temperature, radiation, electromagnetic interference) to determine how other devices fabricated in accordance with the same process technology might react to the same conditions.
Exposure of integrated circuits to nuclear radiation can trigger soft errors (radiation-induced misbehavior). Radiation-induced soft errors are usually categorized as single event transients (SETs) or single event upsets (SEUs). An SET represents a transient change in bit state, while an SEU represents a relatively persistent change in bit state. One conventional soft error detection scheme uses random access memory structures to measure the critical amount of charge needed to flip a bit (Qcrit). Another known technique uses flip-flop chains to measure Qcrit. Existing approaches, however, utilize different test structures or test devices to measure SETs and SEUs. Consequently, such existing solutions are inefficient and costly.
Accordingly, it is desirable to have an efficient and effective semiconductor-based test structure that can detect both SETs and SEUs. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.